VLSI Chip Designs
I began my VLSI career in 1996 by graduating from Clemson with a BS in Computer Engineering. Several years later I recieved my MS in Computer Engineering from Syracuse. My masters topic was in the area of packaging methods. In 2000, I moved to Maryland as an Air Force developmental engineer and designed several chips. I also spent some time in a clean room environment at the University of Maryland as well as the foundry at the National Security Agency.
A summary of my VLSI related work and experience follows:
(NSA-2001) – KGV-135A Encryption Chip. Redesigned an earlier ECL technology chip by using .35u technology. The redesign solved heat problems and increased the operational speed and data handling capability. The KGV-135A was then used as a primary COMSEC device for the "Common Data Link" system used by the USAF, CIA, and other intelligence gathering entities. The redesigned device was physically manufacatured at the National Security Agency Foundry in Maryland. My primary contributions included the VHDL design and verification methods.
(NSA-2003) – KG-70 Encryption Chip. Similar in theory to the KGV-135, the KG-70 was designed to be an ultra low power consumption encryption device meant to be installed in clandestine environements. My contribution towards this project was the VHDL implementation of a polynomial, prime number based encryption algorithm. I also worked closely with a commercial company to develop and utilize the "Raisin" core which provided very close to true random number generation. Additionally, the KG-70 contained a feature that allowed it to go to sleep and consume virtually no power while at the same time maintaining its encryption key. This device gave me my first insight into some of the considerations of very low power devices.
(RRS) – PCIF-2. This device was created as an interface between SDRAM, PCI, a multi-processor bus, and a 16 bit network chip. Because the four interfaces were of different word sizes and did not all use the same clock, large banks of FIFOs were added to the design along with a module to handle multiple non-overlapping dual clock systems. My contribution to this devices was the development of state machine logic, implementation of the FIFOs. All registers included JTAG capability. The coding was performed using VHDL while the logic design was performed using MAGIC and IRSIM. I also performed the pin routing for the device which was interesting because this chip was to be used in an MCM with bump bonds. As there were nearly 400 IO pins, including P&G, this was indeed a challenge. The device was intended to be used in an interceptor ballistic missile.
(RRS) – PCIF. This device was my first true exposure to VLSI design. I worked with a team of 2 other engineers to develop an interface between a PCI bus and a processor bus. Two different clock speeds and a requirment for both 32b and 64b operation made this an interesting design.